1. Field of the Invention
The present invention relates to a drive circuit for a display apparatus, and more particularly to a drive circuit for driving a display section comprising a plurality of parallel signal electrodes and a plurality of parallel scanning electrodes crossing each other, pixel electrodes disposed near the respective crossings of the signal electrodes and the scanning electrodes, and a counter electrode facing the pixel electrodes.
In this specification, a matrix type liquid crystal display apparatus will be described as a typical example of a display apparatus, but this invention can also be applied to drive circuits for other types of display apparatus such as an electroluminescence (EL) display apparatus and a plasma display apparatus.
2. Description of the Prior Art
A conventional matrix type liquid crystal display apparatus is schematically shown in FIG. 7, which comprises a TFT liquid crystal panel 100 using thin film transistors (TFTs) 104 as switching elements for driving pixel electrodes 103 arranged in a matrix. The TFT liquid crystal panel 100 also comprises a plurality of scanning electrodes 101 disposed in parallel to one another, and a plurality of signal electrodes 102 disposed in parallel to one another so as to cross the scanning electrodes 101. The TFTs 104 for driving the pixel electrodes 103 are disposed near the respective crossings of the scanning electrodes 101 and the signal electrodes 102. A counter electrode 105 is disposed facing the pixel electrodes 103. In FIG. 7, the counter electrode 105 is schematically shown, but it is generally a conductive layer formed as a common counter electrode for all of the pixel electrodes. An oscillating voltage is applied to the counter electrode 105 so as to reduce amplitudes of signal voltages applied to the signal electrodes 102. Hereinafter, the oscillating voltage applied to the counter electrode 105 is referred to as a counter voltage.
The TFT liquid crystal panel 100 is driven by a drive circuit including a source driver 2 and a gate driver 3, which are connected to the signal electrodes 102 and the scanning electrodes 101, respectively. The source driver 2 samples analog image signals or analog video signals input thereto, holds the sampled signals, and then applies them to the signal electrodes 102. The gate driver 3 sequentially applies scanning pulses as drive signals to the scanning electrodes 101. Control signals such as timing signals are applied to the source driver 2 and the gate driver 3 by a control circuit 4.
FIG. 6 shows waveforms of scanning pulses supplied to the scanning electrodes 101 in a conventional matrix type liquid crystal display apparatus.
FIG. 3 shows a relationship between a scanning pulse applied to the scanning electrodes 101 and the counter voltage in a conventional drive circuit. As shown in FIG. 3, the scanning pulse takes a high-level value and a low-level value periodically. A period when the scanning pulse takes the high-level value is referred to as a "gate on period". A period when the scanning pulse takes the low-level value is referred to as a "gate off period". The counter voltage is applied to the counter electrode 105 during the gate on period and the gate off period.
Generally, the low-level value of the scanning pulse is lowered so as to ensure that the TFT 104 is completely in off-state during the gate off period. However, when the low-level value of the scanning pulse is excessively lowered, the TFT 104 can not be completely in off-state. As a result, it is difficult to secure the complete off-state of the TFT 104 during the gate off period.
Referring to FIGS. 4 and 5, the above problem will be described in detail. While the counter voltage is applied to the counter electrode 105, a voltage applied to a drain D of the TFT 104 varies by .DELTA.V.sub.x in the following expression: EQU .DELTA.V.sub.x =.+-.V.sub.c /(1+C.sub.GD /C.sub.LC)
wherein .+-.V.sub.c represents the counter voltage which has an oscillating component, C.sub.GD represents a stray capacitance between a gate G and the drain D of the TFT 104, C.sub.LC represents a capacitance between the pixel electrode 103 and the counter electrode 105.
FIG. 5 shows a relationship between a voltage V.sub.g applied to the gate and a drain current I.sub.D. As shown in FIG. 5, an optimal voltage to be applied to the gate to secure a complete off-state of the TFT 104 varies between voltages V.sub.L and V.sub.H. This makes it difficult to set the low-level value of the scanning pulse to the optimal voltage during the gate off period. As a result, since the complete off-state of the TFT 104 can not be secured, a deterioration of the liquid crystal elements occurs, and a reliability of the display apparatus is lowered.
The objective of the present invention is to provide a drive circuit for a display apparatus which ensures that pixel electrodes of the display apparatus are completely put into the non-driving state when the pixel electrodes are not driven (i.e. during the gate off period) and the non-driving state is sustained for a long period, thereby preventing a deterioration of the display apparatus.